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L6598
HIGH VOLTAGE RESONANT CONTROLLER
1

FEATURES
HIGH VOLTAGE RAIL UP TO 600V dV/dt IMMUNITY 50V/ns IN FULL TEMPERATURE RANGE DRIVER CURRENT CAPABILITY: 250mA SOURCE 450mA SINK SWITCHING TIMES 80/40ns RISE/FALL WITH 1nF LOAD CMOS SHUT DOWN INPUT UNDER VOLTAGE LOCK OUT SOFT START FREQUENCY SHIFTING TIMING SENSE OP AMP FOR CLOSED LOOP CONTROL OR PROTECTION FEATURES HIGH ACCURACY CURRENT CONTROLLED OSCILLATOR INTEGRATED BOOTSTRAP DIODE CLAMPING ON Vs SO16, DIP16 PACKAGES
Figure 1. Packages
DIP-16
SO-16N
Table 1. Order Codes
Part Number L6598 L6598D L6598D013TR Package DIP-16 SO-16N Tape & Reel

2
DESCRIPTION
The device is manufactured with the BCD OFF LINE Figure 2. Block Diagram
VS OP AMP 12 + UV DETECTION
technology, able to ensure voltage ratings up to 600V, making it perfectly suited for AC/DC Adapters and wherever a Resonant Topology can be beneficial. The device is intended to drive two Power MOS, in the classical Half Bridge Topology. A dedicated Timing Section allows the designer to set Soft Start Time, Soft Start and Minimum Frequency. An Error Amplifier, together with the two Enable inputs, are made available. In addition, the integrated Bootstrap Diode and the Zener Clamping on low voltage supply, reduces to a minimum the external parts needed in the applications.
H.V. 16 VBOOT
OPOUT OPINOPIN+
5 6 7
BOOTSTRAP DRIVER
HVG DRIVER
15 14
HVG
CBOOT LOAD
OUT Ifmin VREF DEAD TIME 4 Rfmin LVG DRIVER Ifstart VREF + 2 Rfstart CONTROL LOGIC Iss 3 Cf VCO 1 Css
D98IN887A
DRIVING LOGIC
LEVEL SHIFTER
Vs 11 10 GND 8 LVG
Vthe1
+ Vthe2
EN1
9
EN2
June 2004
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Figure 3. Pin Connection
Css Rfstart Cf Rfmin OPOUT OPINOPIN+ EN1
1 2 3 4 5 6 7 8
D98IN888
16 15 14 13 12 11 10 9
VBOOT HVG OUT N.C. VS LVG GND EN2
Table 2. Thermal Data
Symbol Rth j-amb Parameter Thermal Resistance Junction to Ambient SO16N 120 DIP16 80 Unit C/W
Table 3. Pin Function
N. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name CSS Rfstart Cf Rfmin OPout OPonOPon+ EN1 EN2 GND LVG Vs N.C. OUT HVG Vboot Soft Start Timing Capacitor Soft Start Frequency Setting - Low Impedance Voltage Source - See also Cf Oscillator Frequency Setting - see also Rfmin, Rfstart Minimum Oscillation Frequency Setting - Low Impedance Voltage Source - See also Cf Sense OP AMP Output - Low Impedance Sense Op Amp Inverting Input - High Impedance Sense Op Amp Non Inverting Input - High Impedance Half Bridge Latched Enable Half Bridge Unlatched Enable Ground Low Side Driver Output Supply Volatge with Internal Zener Clamp Not Connected High Side Driver Reference High Side Driver Output Bootstrapped Supply Voltage Function
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Table 4. Absolute Maximum Ratings
Symbol IS VLVG VOUT VHVG VBOOT dVBOOT/dt dVOUT/dt Vir Vic Supply Current at Vcl (*) Low Side Output High Side Reference High Side Output Floating Supply Voltage VBOOT pin Slew Rate (repetitive) OUT pin Slew Rate (repetitive) Forced Input Voltage (pins Rfmin, Rfstart) Forced Input Volatge (pins Css, Cf) Parameter Value 25 14.6 -1 to VBOOT -18 -1 to VBOOT 618 50 50 -0.3 to 5 -0.3 to 5 -0.3 to 5 3 -0.3 to 5 -5 to 5 4.6 -40 to +150 -40 to +150 -40 to +125 Unit mA V V V V V/ns V/ns V V V mA V V V C C C
VEN1, VEN2 Enable Input Voltage IEN1, IEN2 Vopc Vopd Vopo Tstg Tj Tamb Enable Input Current Sense Op Amp Common Mode Range Sense Op Amp Differential Mode Range Sense Op Amp Output Voltage (forced) Storage Temperature Junction Temperature Ambient Temperature
(*) The device is provided of an internal Clamping Zener between GND and the Vs pin, It must not be supplied by a low impedance voltage source. Note : ESD immunity for pins 14, 15 and 16 is guaranteed up to 900 (Human Body Model).
Table 5. Recommended Operating Conditions
Symbol VS Vout (*) Vboot (*) fmax Supply Voltage High Side Reference Floating Supply Rail Maximum Switching Frequency Parameter Value 10 to Vcl -1 to Vboot-Vcl 500 400 Unit V V V kHz
(*) If the condition Vboot - Vout < 18 is guaranteed, Vout can range from -3 to 580V.
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Table 6. Electrical Characteristcs (VS = 12V; VBOOT - VOUT = 12V; Tamb = 25C)
Symbol Vsuvp Vsuvn Vsuvh Vcl Isu Iq Pin 12 Parameter VS Turn On Threshold VS Turn Off Threshold Supply Voltage Under Voltage hysteresis Supply Voltage Clamping Start Up Current Quiescent Current, fout = 60kHz, no load 16 14 16 15 11 15,11 BOOT pin Leakage Current OUT pin Leakage Current Bootstrap Driver On Resistance High Side Driver Source Current VHVG-VOUT = 0 High Side Driver Sink Current Low Side Driver Source Current Low Side Driver Sink Current Low/High Side Output Rise Time VHVG-VBOOT = 0 VLVG-GND = 0 VLVG - VS = 0 Cload = 1nF Cload = 1nF 14 Output Duty Cycle Minimum Output Oscillation Frequency Soft Start Output Oscillation Frequency 2, 4 14 Voltage to Current Converters Threshold Dead Time between Low and High Side Conduction Soft Start Timing constant Input Bias Current Input Offset Voltage 5 Output Resistance Source Output Current Sink Output Current 6,7 OP AMP input common mode range Vout = 4.5V Vout = 0.2V -10 200 1 1 -0.2 3 Css = 330nF Cf = 470pF; Rfmin = 50k Cf = 470pF; Rfmin = 50k; Rfstart = 47k 48 58.2 114 1.9 0.2 Vs < Vsuvn Vs > Vsuvp 2 14.6 Test Condition Min. 10 7.3 Typ. 10.7 8 2.7 15.6 16.6 250 3 Max. 11.4 8.7 Unit V V V V A mA SUPPLY VOLTAGE
HIGH VOLTAGE SECTION Ibootleak Ioutleak Rdon Ihvgso Ihvgsi Ilvgso Ilvgsi trise tfall OSCILLATOR DC fmin fstart Vref td 50 60 120 2 0.27 52 61.8 126 2.1 0.35 % kHz kHz V s VBOOT = 580V VOUT = 562V 100 170 300 170 300 150 250 450 250 450 80 40 120 80 5 5 300 A A mA mA mA mA ns ns
HIGH/LOW SIDE DRIVERS
TIMING SECTION kss lIB Vio Rout IoutIout+ Vic 1 6, 7 0.115 0.15 0.185 0.1 10 300 s/F A mV mA mA V SENSE OP AMP
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Table 6. Electrical Characteristcs (continued) (VS = 12V; VBOOT - VOUT = 12V; Tamb = 25C)
Symbol GBW Gdc COMPARATORS Vthe1 Vthe2 tpulse 8 9 8,9 Enabling Comparator Threshold Enabling Comparator Threshold Minimum Pulse lenght 0.56 1.05 0.6 1.2 0.64 1.35 200 V V ns Pin Parameter Sense Op Amp Gain Band Width Product (*) DC Open Loop Gain Test Condition Min. 0.5 60 Typ. 1 80 Max. Unit MHz dB
(*) Guaranted by design
Figure 4. EN2 Timing Diagrams
VS
fOUT
fstart
fmin
EN2
VCss
TSS
TSS
D98IN889
Figure 5. EN1 Timing Diagrams
HVG
LVG
EN1
EN2
D98IN890
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Figure 6. Oscillator/Output Timing Diagram
Cf
HVG
LVG
D98IN897
3
BLOCK'S DIAGRAM DESCRIPTION
3.1 High/Low Side driving section An High and Low Side driving Section provide the proper driving to the external Power MOS or IGBT. An high sink/source driving current (450/250 mA typ) ensure fast switching times also when size4 Power MOS are used. The internal logic ensures a minimum dead time to avoid cross-conduction of the power devices. 3.2 Timing and Oscillator Section The device is provided of a soft start function. It consists in a period of time, TSS, in which the switching frequency shifts from fstart to fmin. This feature is explained in the following description (ref. fig.7 and fig.8). Figure 7. Soft Start and frequency shifting block
Iss
Ifstart
Ifmin
Iosc gm Css OSC
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During the soft start time the current ISS charges the capacitor CSS, generating a voltage ramp which is delivered to a transconductance amplifier, as shown in fig. 7. Thus this voltage signal is converted in a growing current which is subtracted to Ifstart. Therefore the current which drives the oscillator to set the frequency during the soft start is equal to:
g m I ss I osc = I fmin + ( I fstart - g m V Css ( t ) ) = I fmin + I fstart - ------------- t C ss where I fmin = ------------- , I fsart = --------------- , V REF = 2V [2] R fmin R fstart
At the start-up (t=0) the oscillator frequency is set by:
[1]
V REF
V REF
1 1 I osc ( 0 ) = I fmin + I fstart = V REF ------------- + --------------- [3] R fmin R fstart
At the end of soft start (t = TSS) the second term of eq.1 decreases to zero and the switching frequency is set only by Imin (i.e. Rfmin):
V REF I osc ( T ss ) = I fmin = ------------- [4] R fmin
Since the second term of eq.1 is equal to zero, we have:
g m I ss C ss I fstart I fstart - ------------- T SS = 0 T SS = ----------------------- [5] C ss g m I ss
Note that there is not a fixed threshold of the voltage across CSS in which the soft start finishes (i.e. the end of the frequency shifting), and TSS depends on CSS, Ifstart, gm, and ISS (eq. 5). Making TSS independent of Ifstart, the ISS current has been designed to be a fraction of Ifstart, so:
C ss I fstart C ss I fstart I SS = ------------- T SS = ------------------------- T SS = ---------- T SS - k SS C SS [6] K g m I fstart K gm K
In this way the soft start time depends only on the capacitor CSS. The typical value of the kSS constant (Soft Start Timing Constant) is 0.15 s/F. The current Iosc is fed to the oscillator as shown in fig. 7. It is twice mirrored (x4 and x8) generating the triangular wave on the oscillator capacitor Cf. Referring to the internal structure of the oscillator (fig.7), a good relationship to compute an approximate value of the oscillator frequency in normal operation is:
1.41 f min = ------------------- [7] R fmin C f
The degree of approximation depends on the frequency value, but it remains very good in the range from 30kHz to 100kHz (figg.9-13)
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Figure 8. Oscillator Block
Iosc
X4
Vth+
+
S Cf R
Vth-
+
X8
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Figure 9. Typ. fmin vs. Rfmin @ Cf = 470pF
fmin (KHz)
D98IN891
Figure 12. Typ. (fstart-fmin) vs. Rfstar @ Cf = 470pF
f (KHz) 100
D98IN894
100
Rfmin=100K
80
80
60
60
40
40
20 20 40 60 80 100 Rfmin(K)
20 20 40 60 80 100 Rfstart(K)
Figure 10. Typ. (fstart-fmin) vs. Rfstar @ Cf = 470pF
f (KHz)
D98IN892
Figure 13. fmin @ different Rf vs Cf
fmin (KHz)
Rf=19.9Kohm - calc.
80
400
Rfmin=33K
Rf=19.9Kohm - meas.
60
200 Rf=90Kohm - meas.
40
Rf=90Kohm - calc.
20 20 40 60 80 100 Rfstart(K)
0 0 200 400 Cf (pF)
Figure 11. Typ. (fstart-fmin) vs. Rfstar @ Cf = 470pF
f (KHz) 100
Rfmin=50K
D98IN893
80
60
40
20 20 40 60 80 100 Rfstart(K)
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3.3 Bootstrap Section The supply of the high voltage section is obtained by means of a bootstrap circuitry. This solution normally requires an high voltage fast recovery diode for charging the bootstrap capacitor (fig. 14a). In the device a patented integrated structure, replaces this external diode. It is realised by means of a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in fig. 14b. Figure 14. Bootstrap driver
DBOOT
VS VS VBOOT
VBOOT
CBOOT CBOOT
VOUT
LVG
VOUT
a
b
To drive the synchronised DMOS it is necessary a voltage higher than the supply voltage Vs. This voltage is obtained by means of an internal charge pump (fig. 14b). The diode connected in series to the DMOS has been added to avoid undesirable turn on of it. The introduction of the diode prevents any current can flow from the Vboot pin to the VS one in case that the supply is quickly turned off when the internal capacitor of the pump is not fully discharged. The bootstrap driver introduces a voltage drop during the recharging of the capacitor Cboot (i.e. when the low side driver is on), which increases with the frequency and with the size of the external power MOS. It is the sum of the drop across the RDSON and of the diode threshold voltage. At low frequency this drop is very small and can be neglected. Anyway increasing the frequency it must be taken in to account. In fact the drop, reducing the amplitude of the driving signal, can significantly increase the RDSON of the external power MOS (and so the dissipation). To be considered that in resonant power supplies the current which flows in the power MOS decreases increasing the switching frequency and generally the increases of RDSON is not a problem because power dissipation is negligible. The following equation is useful to compute the drop on the bootstrap driver:
Qg V drop = I ch arg e R dson + V diode V drop = ------------------ R dson + V diode [8] T ch arg e
where Qg is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the time in which the bootstrap driver remains on (about the semiperiod of the switching frequency minus the dead time). The typical resistance value of the bootstrap DMOS is 150 Ohm. For example using a power MOS with a total gate charge of 30nC the drop on the bootstrap driver is about 3V, at a switching frequency of 200kHz. In fact:
30nC V drop = ------------------ 150 + 0.6V~2.6V 2.23s
To summarise, if a significant drop on the bootstrap driver (at high switching frequency when large power MOS are used) represents a problem, an external diode can be used, avoiding the drop on the RDSON of the DMOS.
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3.4 OP AMP Section The integrated OP AMP is designed to offer Low Output Impedance, wide band, High input Impedance and wide Common Mode Range. It can be readily used to implement protection features or a closed loop control. For this purpose the OP AMP Output can be properly connected to Rfmin pin to adjust the oscillation frequency. 3.5 Comparators Two CMOS comparators are available to perform protection schemes. Short pulses (>= 200ns) on Comparators Input are recognised. The EN1 input (active High), has a threshold of 0.6V (typical value) forces the device in a latched shut down state (e.g. LVG Low, HVG low, Oscillator stopped), as in the Under Voltage Conditions. Normal Operating conditions are resumed after a power-off power-on sequence. The EN2 input (active high), with a threshold of 1.2V (typical value) restarts a Soft Start sequence (see Timing Diagrams). In addition the EN2 Comparator, when activated, removes a latched shutdown caused by EN1. Figure 15. Switching Time Waveform Definitions
90% 90%
HVG
10% tr tf
10%
90%
90%
LVG
10% tr tf
10%
D98IN898
Figure 16. Dead Time and Duty Cycle Waveform Definition
T1 td td Dc = T1 Tperiod
50% HVG
50%
50% LVG
50%
50%
Tperiod
D98IN899
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Figure 17. Typ. fmin vs. Temperature
fmin (KHz)
D98IN895
Figure 20. Start Up Current vs Temperature
Isu (A)
70
200
60
150
50
100
40 -50 0 50 100 T(C)
50 -50 0 50 100 T (C)
Figure 18. Typ. fstart vs. Temperature
ffstart (KHz)
D98IN896
Figure 21. Quiescent Current vs Temperature
Iq (mA) 2.3
130
2.1
Iq @ Vclamp
120
1.9
Iq @ 12V
110
1.7
100 -50 0 50 100 T(C)
1.5 -50 0 50 100 T (C)
Figure 19. Vs thresholds and clamp vs temp.
Vs (V) Vclamp 14
Figure 22. HVG Source and Sink Current vs. Temperature
Ihvg (mA)
500
12
400
Vsuvp
10
Ihvg sink curr. 300
8 Vsuvn
200
Ihvg source curr.
6 -50 0 50 100 T (C)
100 -50 0 50 100 T (C)
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Figure 23. LVG Source and Sink Current vs. Temperature
Ilvg (mA)
Figure 24. Soft Start Timing Constant vs. Temperature
kss (s/F)
500
400 Ilvg sink curr. 300
0.16
0.14 200 Ilvg source curr.
100 -50 0 50 100 T (C)
0.12 -50
0
50
100
T (C)
Figure 25. Wide Range AC/DC Adapter Application
85 to 270 Vac
L6561/2
Vo
L6598
DRIVER VCO & CONTROL TL431
ENABLE
D98IN874A_MOD2
13/17
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Figure 26. DIP-16 Mechanical Data & Package Dimensions
mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP. MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 inch TYP. MAX.
DIM.
OUTLINE AND MECHANICAL DATA
DIP16
0.050
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Figure 27. SO-16N Mechanical Data & Package Dimensions
mm DIM. MIN. A a1 a2 b b1 C c1 D(1) E e e3 F(1) G L M S 3.8 4.60 0.4 9.8 5.8 1.27 8.89 4.0 5.30 1.27 0.62 8 (max.) 0.150 0.181 0.150 0.35 0.19 0.5 45 10 6.2 (typ.) 0.386 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.394 0.244 0.1 TYP. MAX. 1.75 0.25 1.6 0.46 0.25 0.014 0.007 0.020 0.004 MIN. TYP. MAX. 0.069 0.009 0.063 0.018 0.010 inch
OUTLINE AND MECHANICAL DATA
SO16 (Narrow)
(1) "D" and "F" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (.006inc.)
0016020 D
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Figure 28. Revision History
Date June 2004 Revision 5 Description of Changes Changed the impagination following the new release of "Corporate Technical Pubblication Design Guide". Done a few of corrections in the text.
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved
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